The present invention relates to an interconnect structure of a semiconductor integrated circuit having air gaps in submicron processes, and a design method and device for the same.
In recent years, with achievement of finer semiconductor processes, the integration of semiconductor integrated circuits has become significantly higher. Higher integration however extremely narrows the spacing between interconnects, causing a problem of increase in parasitic capacitance between interconnects. The increase in parasitic capacitance between interconnects will result in occurrence of a crosstalk phenomenon in which an electric signal leaks between interconnects, increase of a RC delay of interconnects and increase of power consumption.
In view of the above, in the field of semiconductor fabrication technologies, studies are being made vigorously on an interlayer insulating film low in dielectric constant (low-k film) that reduces the parasitic capacitance between interconnects, with an eye toward the under 45 nm process. Besides the studies on the low-k film, an interconnect structure has been proposed in which voids (hereinafter, called air gaps) are intentionally formed of the air in an insulating film between interconnects (see Japanese Patent Gazette No. 2087547 [Patent Literature 1], for example). Such air gaps using the air whose dielectric constant is 1 are argued to give a further low relative dielectric constant than the low-k film.
As a fabrication method in which air gaps are generated, a conventional technology is known in which after insertion of a metal layer in an insulating film, air gap generation positions are etched using a resist pattern masking air gap exclusion areas. It is proposed to designate a region around a via as an air gap exclusion area to prevent an air gap from communicating with the via due to an alignment deviation that may occur during semiconductor fabrication (see Japanese Laid-Open Patent Publication No. 2006-120988 [Patent Literature 2], for example).
Air gaps are voids generated because the material of an insulating film to be deposited on a metal layer has failed to flow into the positions of the voids. The open width of such voids has an upper limit for allowing generation of air gaps depending on the material of the insulating film. For this reason, as a design method for an interconnect structure of a semiconductor integrated circuit, proposed has been a technology of reducing the interconnect spacing by adding a dummy pattern to thereby increase the number of air gaps (see Japanese Patent Gazette No. 3481222 [Patent Literature 3], for example).
However, the conventional ways of generating air gaps have the following problems.
First, no consideration has been given to a detriment that may result from imprudent reduction of the parasitic capacitance between interconnects. In the under 180 nm process, hold timing errors occur frequently because of increase in the propagation time lag of a clock signal (clock skew) caused by crosstalk, IR drop, operation conditions and the like. Air gaps generated without consideration of a delay will further increase the hold timing error. Patent Literature 3, in which a dummy pattern is formed to ensure interconnect spacing of a given value or less so as to generate as many air gaps as possible, has this problem. Also, the reduction in capacitance between power supply traces will cause power supply noise.
Secondly, in design of a semiconductor integrated circuit, routing considering air gap-caused capacitance reduction has not been made. While the interconnect delay can be reduced with the air gap-caused capacitance reduction, a huge number of steps will be consumed for timing convergence.
Thirdly, in Patent Literature 2, in which a resist pattern for exclusion of generation of air gaps is generated, as the number of exclusion positions increases and thus the graphic data amount increases, the OPC processing time will increase. This also applies to the case of generating a pattern for designating positions for formation of air gaps.
Fourthly, no consideration has been given to a possibility that an air gap may pass through an overlying insulating film depending on the size of the air gap. Air gaps have a cone-shaped upper portion due to deposition of the insulating film. If the interconnect spacing in which an air gap is formed is so large that the cone-shaped portion of the air gap becomes high in level, the apex of the air gap may possibly be shaved off during grinding of the insulating film. An overlying film may flow into the resultant void causing reduction in yield.
Fifthly, in Patent Literature 2, a region around a via is designated as an air gap exclusion area to avoid an air gap from communicating with the via. With several millions to several tens of millions of vias formed on one chip, search for vias is complicate in form ation of air gap exclusion areas, and this increases the processing time.